The invention relates to semiconductor memory structures and processes for forming semiconductor memory structures.
Present trends in DRAM technology are constantly driving towards reduction in minimum feature size, F, and more compact cell layouts. It follows that array densities are also ever increasing. The decreasing size of memory structures as well as the increasing array density can result in problems in the fabrication of memory structures and in the operation of the memory structures. Various structures and methods have been proposed to address the manufacturing and operational problems associated with smaller and denser memory cell structures.
The present invention provides a memory cell structure. The memory cell structure includes a planar semiconductor substrate. A deep trench is arranged in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is arranged at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has an upper source/drain diffusion and a lower source/drain diffusion extending in the plane of the substrate adjacent the deep trench. An isolation region extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and connected to the gate conductor. A bitline extends above the surface plane of the substrate having a contact to the source diffusion between the shallow trench isolation regions.
Additionally, the present invention provides a process for forming a memory cell structure. A deep trench is formed having a plurality of side walls in a planar semiconductor substrate. A storage capacitor is formed at the bottom of the deep trench. A vertical transistor is formed extending down at least one side wall of the deep trench above the storage capacitor. The transistor is formed having upper source/drain diffusions and lower source/drain diffusions extending in the plane of the substrate adjacent the deep trench. An isolation region is formed extending down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions are formed extending along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor is formed extending within the deep trench. A wordline is formed extending over the deep trench and connected to the gate conductor. A bitline is formed extending above the surface plane of the substrate having a contact to the source diffusion between the shallow trench isolation regions.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.